Feasibility of a Pass Transistor Logic Library for General Purpose ASIC Design

CMOS has dominated the digital design space almost since its discovery. Alternative design styles such as domino logic, complementary pass gate logic, and others have been proposed and implemented, but none achieved the penetration and reach of the standard CMOS library. These other designs often have benefits for certain applications but none have been able to unseat CMOS as the de facto design style. This project examines the feasibility of moving one of these design styles, a custom pass transistor logic library (PTL) with restoring logic, into the same general purpose environment that its CMOS counterpart currently dominates. This study was conducted using the Cadence EDA Suite using the venerable .5 micron AMI design rules. This process is employed by the University of Utah for most student design projects and fabrication is still possible through such Fabrication companies as MOSIS. These reasons, as well as the authors' prior experience with this process, were the deciding factors for choosing this technology node and design suite. It is the authors' thought that this study could be reproduced using present and future technology nodes just as the 90 and 65nm processes and smaller given the proper access to these technologies spice files and design rules. This topic will be revisited under the possible future work section of this paper. This paper shows comparative results of PTL and CMOS versions of an AOI, XOR, Inverting MUX, NAND, NOR and NOR4. More gates would have been tested, but many of the results were easily inferred by looking at the results of similar cells and the trends that began to appear as these six gate structures were examined. The PTL cells almost universally were smaller than their CMOS counterparts, but the performance and power results were not as clear cut.